1. Field of the Invention
The present invention relates to a semiconductor device having an input circuit in which a change of a logic threshold voltage is suppressed.
Priority is claimed on Japanese Patent Application No. 2009-286383, filed Dec. 17, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
In semiconductor devices such as a central processing unit (CPU) and a dynamic random access memory (DRAM), an amplitude of an input signal input from the outside becomes low due to a decrease in an operating power supply voltage. That is, if a high potential side of the amplitude of the input signal is set to VIH and a low potential side thereof is set to VIL, a difference (VIH−VIL) is small. An input circuit (input buffer) to which the input signal is input has a logic threshold voltage. If VIH is higher than the logic threshold voltage, the input signal is sensed as an H level (logic “1” level). If VIL is lower than the logic threshold voltage, the input signal is sensed as an L level (logic “0” level).
Thus, the logic threshold voltage of the input circuit is designed to be set to a specified value substantially intermediate between VIH and VIL, but VIH/VIL of the input signal may not be accurately sensed if the logic threshold voltage is shifted from the specified value by a process variation, a temperature change, or the like when (VIH−VIL) decreases.
To solve this problem, a technique has been disclosed to adjust a logic threshold voltage in correspondence with a level of an input signal using a ring oscillator in a semiconductor device disclosed in Japanese Unexamined Patent Application, First Publication, No. 6-85652.